Device scaling limits of Si MOSFETs and their application dependencies. Energy-efficient abundant-data computing: the N3XT 1,000X. Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI.
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The 300 mm silicon wafer-a cost and technology challenge. Design of ion-implanted MOSFET’s with very small physical dimensions. We demonstrate uniform and reproducible CNFET fabrication across industry-standard 200 mm wafers, employing the same equipment currently being used to fabricate silicon product wafers.ĭennard, R. This allows us to fabricate CNFETs in a commercial silicon manufacturing facility and high-volume semiconductor foundry. By elucidating the mechanisms driving nanotube deposition, we develop process modifications to standard solution-based methods that significantly improve throughput, accelerating the deposition process by more than 1,100 times, while simultaneously reducing cost. Here, we show that a deposition technique in which the substrate is submerged within a nanotube solution can address these challenges and can allow CNFETs to be fabricated within industrial facilities. Such a deposition method needs to be manufacturable, compatible with today’s silicon-based technologies, and provide a path to achieving systems with energy efficiency benefits over silicon. A critical challenge in transferring this technology to commercial manufacturing facilities is developing a suitable method for depositing nanotubes uniformly over industry-standard large-area substrates. Despite rapid progress, CNFETs have only been fabricated in academic or research laboratories.
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Carbon nanotube field-effect transistors (CNFETs) are a promising nanotechnology for the development of energy-efficient computing.